AMD has their own version of this remote management stuff. Who knows what’s lurking there.
The only thing that doesn’t have all this baggage these days will probably at first come from the ARM or POWER-based systems. As those are going to be running on SoC’s that’s less adulterated with the enterprise-thought fever that caused Intel/AMD to put in the IME/AMT in the first place.
A little off topic but in the interest of free and open computing. I would like to direct your attention to two noteworthy open source projects that can mitigate issues like this in the future. Just as open-source (and to a large extent free software, as in GPL) operating systems gave us the ability to run whatever we want on our computer. These projects provide somewhat of an analog to open source/free CPUs:
- RISC-V (https://riscv.org/)
- J2/J4 Cores (http://j-core.org/)
Both of these projects are Open Source CPUs for FPGA/ASIC solutions. In the case of RISC-V, there are several vendors that are making dedicated chips using the design.
I bring these up because a truly open source computer would require no hidden, proprietary components that bugs and backdoors can be hidden in. It also necessarily needs to have support for users to upgrade and patch any bugs or vulnerabilities.
The J2 Core is aimed at very low-end, low-RAM, and low resource environments with a MMU-less CPU, but running Linux. You can watch Linux Foundation talk on JCore here: (https://youtu.be/lZGHbMS882w). There are later talks where they demo the J2 Core on a board you can already buy for $50. They are supposed to be making a J4 Core based on the SH4 (with MMU support), etc. The project is in VHDL.
The RISC-V processor is a family of processors designed in UC Berkley. It is an open source family of processors that are more sophisticated. Some forms are just microprocessors and others can be a full multi-staged pipelined out of order execution CPU like any modern ARM processors. The starting cost of this project is a lot higher. You will need to bring your own FPGA devkit (and some of the reference design costs in the $100 if not $1000s). The project is written in Chisel, which is a domain-specific dialect of Scala.
Both are very worthy efforts if you have the expertise, interesting, or funding to support.
</ digression >